The present invention relates to a method for fabricating a MOSFET having a gate channel of a predetermined, very small channel length.
With conventional technologies, it is only with difficulty that transistors having gate channel lengths of below 100 nm, so-called short-channel transistors in the sub-: range, can be fabricated so exactly that the required electrical operating parameters are complied with. A high performance of the transistor presupposes, for example, a high operating current with a low power consumption and also only a low leakage current in the off state. Furthermore, the gate resistance and parasitic effects such as the Miller capacitance are intended to be as small as possible.
This requires dimensionally accurate dimensions and proportions of the transistor, which is formed by the sequence of many process steps. Particular difficulties are posed at the present time by the fabrication of T-shaped gate layer stacks whose lower layer, in accordance with the desired channel length, is very narrow in comparison with the upper layer of the gate layer stack.
Various methods have been proposed for fabricating T-gate transistors. Thus, e.g. the fabrication of a T-gate in which a metal layer is subsequently deposited onto a preformed polysilicon gate is known. On account of positional errors between the layers, however, it is necessary to increase the distance between the source/drain contacts and the gate in order to ensure entirely satisfactory operation of the transistor even in the event of a misalignment. However, this entails an increased source/drain resistance.
A short-channel transistor is described e.g. by Ghani, Ahmed et al., IEDM 99, page 415. Furthermore, D. Hisamoto et al. (IEEE Transaction on Electronic Devices, Vol 44, 6, 97, page 951) describe a method for fabricating a self-aligned T-gate with a tungsten layer on an underlying first gate layer.
Moreover, Kasai et al. (IEDM 94, pages 497-98) describe a method for fabricating a T-gate in which the gate layer stack comprises polysilicon, a diffusion barrier and a metal layer deposited one above the other.
It is disadvantageous in the latter methods that the short-channel gate has to be structured with the aid of complicated lithographic methods, for instance with the aid of an electron beam.
It is accordingly an object of the invention to provide a method for fabricating a MOSFET with very small channel length which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the method enables a T-gate transistor with a very short channel length to be fabricated dimensionally accurately, in a very simple manner and cost-effectively.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a MOSFET with a gate channel of a predetermined, very small channel length. The method comprises the following steps:
producing a dielectric on a semiconductor substrate;
applying a first gate layer to the dielectric, the first gate layer comprising polysilicon;
forming an intermediate layer, preferably of tungsten nitride, to serve as a diffusion barrier, on the first gate layer;
applying a second gate layer, the second gate layer comprising tungsten;
masking the second gate layer to define a width of the second gate layer to be greater than the predetermined channel length;
anisotropically etching the second gate layer, the intermediate layer, and the first gate layer;
isotropically laterally undercutting the first gate layer under the second gate layer selectively with respect to the dielectric, with respect to the intermediate layer, and with respect to the second gate layer, thereby utilizing an etching gas containing hydrogen bromide in a dry etching process, and controlling the etching process for forming the first gate layer with a predetermined width less than the width of the second gate layer and corresponding to the predetermined channel length.
According to the invention, various etching steps having different degrees of isotropy are combined with one another in a suitable manner in order to obtain the desired T-shaped structure of the gate. Firstly, the gate layer stack is etched anisotropically, thereby patterning it. The gate thus formed is still significantly wider than the predetermined channel length.
In contrast to conventional methods, there is no attempt firstly to form a lower gate layer with the same width as the predetermined channel length, rather, according to the invention, firstly a layer stack is produced which is wider and can therefore be formed with the aid conventional inexpensive lithography steps. This makes the method particularly cost-effective.
Firstly, the second gate layer is masked in such a way that its width is greater than the predetermined channel length; i.e. the masking is effected in such a way that after the hereinafter first etching step, a layer stack is produced which comprises the first and second gate layers and has a width which is greater than the predetermined channel length.
The further processing of the gate layer stack in order to achieve the small gate length corresponding to the predetermined channel length is then effected by subsequent etching of the lower gate layer from the side.
To that end, according to the invention, a second etching step is carried out. In order to reach the first gate layer concealed by the second gate layer, the second etching is carried out isotropically. On account of this isotropy, the second etching brings about a lateral constriction of the first gate layer, which is narrowed in a controlled manner down to the predetermined channel length. In this case, the short-channel gate thus obtained is produced with the aid of simple process steps known per se, without complicated methods being employed.
A preferred embodiment provides for the width of the first gate layer to be controlled by the width of the second gate layer and by the duration of the controlled lateral undercutting of the first gate layer under the second gate layer. In the simplest case, the concentration of etchants and other parameters of the undercutting remain constant, so that only the time duration of this etching determines the lower gate length. In this case, the predetermined width of the first gate layer is preferably equal to the predetermined channel length.
One development of the invention provides for the width of the first gate layer to be controlled during the undercutting with the aid of the concentration of an etchant. In this case, the concentration can be set to a value which is constant during the etching, or else be altered in the course of the etching.
The predetermined width of the first gate layer is preferably equal to the predetermined channel length. On the other hand, deviations of 10% in both directions also still lie within the scope of the invention.
It is preferably provided that the anisotropic etching of the second and of the first gate layer is continued until the dielectric is reached. The sidewall produced during the isotropic etching becomes particularly uniform as a result. On the other hand, the first, isotropic etching can also be ended within the lower gate layer and the second, isotropic etching can be begun there. In this case, the dielectric is not reached until during the second etching.
Finally, it is provided that the first gate layer is isotropically laterally undercut selectively with respect to the second gate layer. As a result, the upper dimensions of the gate line are preserved and can thus be contact-connected more easily.
The undercutting is preferably carried out with the aid of an isotropic plasma etching step. In this case, conventional dry etching chambers with inductive or other coupling-in are implied.
A hydrogen halide preferably serves as etching gas for the isotropic etching; hydrogen bromide, in particular, is advantageous owing to its good selectivity with respect to metals.
With regard to the dimensions of the T-gate that is fabricated, preferred embodiments provide for the width of the second gate layer to be between 120 and 300 nm and for the width of the first gate layer to between 30 and 150 nm. Transistors having a channel length of 30 to 150 nm are thus preferably fabricated.
The gate dielectric preferably contains silicon dioxide.
The second gate layer preferably has a higher electrical conductivity than the first gate layer. As a result, the overall conductivity of the gate is increased. The second gate layer preferably comprises tungsten as metal. It can be composed of tungsten.
One development of the invention provides for the introduction of source/drain implantations and the diffusion thereof under the predetermined width of the second gate layer as far as the edge of the first gate layer. In this case, the wider, upper gate layer forms part of a mask which allows the implantations to be introduced into the wafer only at a certain distance from the lower gate layer through the dielectric. The subsequent thermal distribution of the implantations is controlled in such a way that the dopants likewise cover, in addition to the width of a spacer, the difference between the widths of the second and first gate layers, i.e. the path to the predetermined small channel length.
In a preferred implementation, the MOSFET according to the invention forms a part of a DRAM or of a logic circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a MOSFET having a very small channel length, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.